Английский
B2 — Upper-IntermediateB2 — Upper-Intermediate
The Design Implementation for Customers using Structured ASIC technology (eASIC) Team within Intel's Programmable Solutions Group (PSG) is looking for a senior level ASIC Engineer.
As a senior level ASIC Engineer, you will interact with customers to collect information on RTL and IP and implement the customer code through synthesis, PnR, timing closure, and hand off layout database to the tape out team.
Qualifications
- 5+ years of experience with RTL (Verilog, SystemVerilog, VHDL), Synthesis (using Design Compiler), Static Timing Analysis (using PrimeTime).
- Bachelor's Degree in Electrical Engineering, Computer Engineering or related field.
- Synopsys Design Constraints for synthesis and timing signoff.
Will be considered as a plus:
- 2+ years of experience using Spyglass including clock domain crossing (CDC) analysis.
- Experience in Design Verification (DV) using standard simulators (e.g. VCS, QuestaSim, NCSim).
- Experience with Structured ASIC implementation design flow.
We offer
- Work in a dynamically developing area.
- Solving interesting applied problems used in real world-class projects, the opportunity to see the result of your work, how it works and is applied in practice.
- High professional level of employees, experts with a worldwide reputation and many years of experience.
- Opportunity to do research together with representatives of teams from other countries, speak at professional conferences.
- Open and friendly atmosphere in the team, comprehensive support.
Яна Федоренко IT Recruiter
