DSP Engineer

About the role

We are looking for a Senior Engineer to take full ownership of the mathematical modeling of a point-to-point HF communication channel — a technically unique challenge tackled by only a handful of specialists in the world. You will work at the intersection of signal processing theory and real RF system design, building models and algorithms that go directly into hardware implementation.

Responsibilities

• Developing mathematical models of the HF communication channel, transmitter, and receiver in MATLAB/Python.
• Modeling QPSK modulation/demodulation and spectral shaping with RRC filters.
• Designing a digital downconverter (NCO, complex mixer, CIC/FIR).
• Developing frequency, phase, and symbol synchronization algorithms, including a Costas loop-based AFC.
• Building a preamble/header correlator and bit-stream recovery logic.
• Modeling Viterbi/FEC decoding and channel distortions: noise, delay, Doppler, multipath.
• Simulating a radio link by coordinates and route parameters; estimating range, noise immunity, and link quality.
• Preparing algorithm specifications and parameter recommendations for subsequent FPGA implementation.
• Mentoring middle engineers and conducting code and architecture reviews.

You are an ideal candidate if you have

• Deep knowledge of DSP: FIR/IIR filters, FFT, polyphase structures, resampling, decimation/interpolation, fixed- and floating-point arithmetic.
• Hands-on experience developing DSP algorithms for radio systems/SDR: receive and transmit chains, DDC/DUC, channel filtering, AGC, squelch, spectral analysis.
• Practical experience with HF communications: signal propagation, fading, selective fading, impulsive and industrial interference, narrowband and wideband noise.
• Experience implementing and optimizing modulation/demodulation: CW, FSK, BPSK/QPSK, digital radio protocols.
• Knowledge of synchronization algorithms: carrier recovery, timing recovery, AFC, PLL, frequency/phase offset correction.
• Experience with noise reduction and interference mitigation: noise blanker, notch filtering, adaptive filtering, interference detection.
• Understanding of IQ signals and practical SDR challenges: IQ imbalance, DC offset, phase noise, dynamic range, aliasing, spurious suppression.
• Proficiency in MATLAB/Simulink or Python (NumPy/SciPy) for algorithm prototyping and analysis.
• Experience verifying algorithms on real RF/IQ data and building automated test benches.

Nice to have:

• FPGA/HDL at DSP-team collaboration level.
• Confident with Linux, Git, CI/CD, and task tracking systems.
• MSc or PhD in Electrical Engineering, Telecommunications, Applied Mathematics, or related field.
• Knowledge of RF subsystems: antennas, amplifiers, transmitters, receivers.

What we offer

• Full ownership of the channel model — from design to FPGA handoff.
• No legacy code. Free choice of tools and technologies. Lean, flexible development process.
• Your algorithms go into real hardware. Direct influence on product outcomes.
• Comfortable office in Dubai with relocation support, 5/2 schedule.
• High-autonomy environment with fast feedback and no bureaucracy.